High speed DRAM (such as for mobile device applications) uses Frequency Set Points (FSPs) to operate the DRAM IO pins in a wide range of frequencies. Two operating points (FSP0 and FSP1) are offered and System-on-Chip (SoC) can use either one of them based on the frequency of operation to control communication between the SoC and the DRAM through the IO pins. For example, FSP0 may encompass operations from 0 to 1 GHz while FSP1 may encompass operations from 1 GHz to 2 GHz. This enables multiple operating settings with each fine-tuned for a particular band of frequency. Currently, the standard operation of FSPs is guided by the JEDEC JESD209-4 LPDDR4 industry standard. At power-up, the SoC defaults to FSP0 that has the default settings to operate in un-terminated, low frequency environments. A specific FSP switch sequence is required to transfer between the FSPs during a clock frequency switch.
In a multi core processor system that uses DRAM as the system memory, DRAM is often used to store crash logs in an event of a catastrophic event that causes the system to shut down. These events are typically triggered by an expired watchdog timer (hardware or software based) in the system or a manual application of a reset switch. The system needs to flush out the crash log into the DRAM and reset the SoC to later read out the crash log back for further debugging investigations. During this system flush, DRAM is put into a Self-Refresh (SR) state during the SoC reset to maintain the DRAM contents. When the SoC gets reset, it goes into a power-up state at which it thinks the DRAM is at FSP0. The system crash could have happened at any given frequency, thus the DRAM could be at FSP0 or FSP1. This mismatch between SoC and DRAM on the FSP setting will cause the SoC to lose reliable communication with DRAM due to IO setting mismatches (On Die Termination (ODT) signals, driver strength etc.). This mismatch prevents the DRAM from being brought out of self-refresh and resetting the FSP using a mode register write command. In such an event, the crash logs residing in DRAM are lost, which severely impacts debugging and root cause analysis of the system event that caused the crash. JEDEC JESD209-4 LPDDR4 currently does not have a process to address this problem.
Accordingly, there is a need for systems, apparatus, and methods that improve upon conventional approaches including the improved methods, system, and apparatus provided hereby that aid in preventing a FSP mismatch during a reset event.